学术报告

题目：Dynamic Tuning for Speculation Threads: Energy and Performance Perspectives

报告人：Dr. Antonia Zhai, Computer Science and Engineering Department, University of Minnesota

时间：2011年6月16日下午3: 00-4: 30

地点：西一楼电信学院第一会议室（344室）

邀请人：赵银亮，计算机系教授

Abstract:

Computer industry has adopted multi-threaded and multi-core architectures as the clock rate increase stalled in early 2000's. In response to the emergence of these new architectures, various novel and sophisticated execution models have been introduced to exploit parallelism at various granularities. One such execution model is Thread-Level Speculation (TLS), which allows potentially dependent threads to execute speculatively in parallel. While successful speculation can speedup otherwise non-parallel applications, unsuccessful speculation can potentially cause significant performance degradation. Furthermore, the potential degradation in energy efficiency also hinders the deployment of this technique. Thus, extracting efficient speculative threads is a real challenge. This task is further complicated by the fact that the performance and energy efficiency of speculative threads is often architecture-dependent, input-sensitive, and exhibits phase behaviors.

In this talk, I will present our approaches for dynamic determining how to best extract speculative parallel threads to improve both performance and energy-efficiency of sequential applications. Our technique features a runtime optimization engine that dynamic extracts and allocates threads in a same-ISA heterogeneous multicore environment.

Biography:

Antonia Zhai is an assistant professor in the Department of Computer Science and Engineering at the University of Minnesota. She received her Ph.D. degree in Computer Science from Carnegie Mellon University in 2005. Prior to that, she received her B.A.Sc. and M.A.Sc. degrees in Computer Engineering from the University of Toronto in 1996 and 1998 respectively. Her research interests include computer architectures, compiler optimizations, and operating systems. In particular, she is interested in the design, implementation and evaluation of novel compiler optimizations and architecture features for the emerging multi-core processor technology. Her research goal is not only to improve the performance for such processor, but also to enhance non-performance features, such as programmability, security, testability and reliability.